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ADC ADC-318, ADC-318A C
OBSOLETE PRODUCT
FEATURES
8-Bit, 120MHz and 140MHz 8-Bit, 120MHz and 140MHz Full-Flash A/D Converter 0 n M
Contact Factory for Replacement Model
Low power dissipation (960mW max.) n W TTL compatible output Diff./Integral nonlinearity (1/2LSB max.) 1:2 Demultiplexed straight output programmable 2:1 Frequency divided TTL clock output with reset Surface mount package Selectable Input Logic (TTl, ECL, PECL) +5V or 5V Power Supply Operation
INPUT/OUTPUT CONNECTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FUNCTION -DVs (Digital) REF. BOTTOM (VRB) ANALOG GROUND REF. MID POINT (VRM1) +AVS (Analog) ANALOG IN (VIN) REF. MID POINT (VRM2) +AVS (Analog) REF. MID POINT (VRM3) ANALOG GROUND REF. TOP (VRT) DIGITAL GROUND 3 A/D CLOCK ECL/PECL A/D CLOCK ECL/PECL A/D CLOCK TTL NO CONNECTION NO CONNECTION NO CONNECTION +DVS2 (Digital) DIGITAL GROUND 2 B BIT 8 (LSB) B BIT 7 B BIT 6 B BIT 5 PIN 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 FUNCTION RSET ECL/PECL RSET ECL/PECL RSET TTL SELECT INV TTL CLOCK OUT +DVS2 (Digital) DIGITAL GROUND 2 A BIT 1 (MSB) A BIT 2 A BIT 3 A BIT 4 A BIT 5 A BIT 6 A BIT 7 A BIT 8 (LSB) DIGITAL GROUND 2 +DVS2 (Digital) +DVS1 (Digital) DIGITAL GROUND 1 B BIT 1 (MSB) B BIT 2 B BIT 3 B BIT 4
GENERAL DESCRIPTION
The ADC-318 and ADC-318A are 8 bit monolithic bipolar, full flash A/D converters. Though they have high, 120MHz (ADC-318) and 140MHz (ADC-318A), sampling rates, their input logic level, including the start convert pulse, is TTL, ECL and PECL compatible. Digital outputs are also TTL compatible and allow a straight output or a programmable 1:2 de-multiplexed output. The ADC-318 and ADC-318A feature 1/2 LSB max. integral and differential non-linearity, +5V single or 5V dual power supply operation, a low 960mW maximum power dissipation, 150MHz wide analog input range and excellent temperature coefficient in a small 48 pin QFP package. The start convert pulse can have a 50% duty cycle. The ADC-318 and ADC-318A offer low cost, easy to use functionality for design engineers.
VIN
6
44 INV 33 BIT 8 (LSB)
VRT 11
6 A TTL OUTPUT
34 BIT 7 35 BIT 6 8 A LATCH 8 36 BIT 5 A OUTPUT 37 BIT 4 38 BIT 3
VRM3 9 6
6-BIT LATCH AND ENCODER COMPARATOR RESISTOR MATRIX ENCODER
39 BIT 2 40 BIT 1 (MSB)
VRM2 7
256
6
21 BIT 8 (LSB) 22 BIT 7
VRM1 4 B LATCH VRB 2 6 6 B TTL OUTPUT
23 BIT 6 24 BIT 5 B OUTPUT 25 BIT 4 26 BIT 3 27 BIT 2 28 BIT 1 (MSB)
A/D CLOCK ECL/PECL 13 A/D CLOCK ECL/PECL 14 A/D CLOCK TTL 15
DELAY
D
Q Q
SELECT
43 CLOCK OUT TTL 45 SELECT
RSET ECL/PECL 48 RSET ECL/PECL 47
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RSET TTL 46
Figure 1. ADC-318/318A Functional Block Diagram
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MDA_ADC-318.B01 Page 1 of 8
ADC-318, ADC-318A
ABSOLUTE MAXIMUM RATINGS
PARAMETERS Supply Voltage (+AVS, +DVS, 1,2) Supply Voltage (AGND, DGND 1, 2) Supply Voltage (DGND 3) Supply Voltage (-DVS) Supply Voltage (-DVS) Reference Voltage (VRT) Reference Voltage (VRB) Reference Voltage (VRT-VRB1) Input Voltage, analog (VIN) Input Voltage, digital ECL PECL TTL Diff. Voltage between Pin Power Dissipation, max. LIMITS -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -7.0 to +0.5 +2.7 to +AVS VIN -2.7 to +AVS 2.5 VRT -2.7 to +AVS -DVS to +0.5 -0.5 to DGND3 -0.5 to +DVS1 2.7 2 UNITS Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts Volts W
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
ADC-318 ADC-318A A/D Clock Pulse Width (TPW0) ADC-318 ADC-318A RSET Setup Time (Trs) RSET Hold Time (Trh) DIGITAL OUTPUTS Output Voltage "1" (@-2mA) Output Voltage "0" (@1mA) Output Rise Time (Tr) Output Fall Time (Tf) Output Delay (Tdo1) Output Delay (Tdo2) Clockout Output Delay (Tdclk) PERFORMANCE Resolution Conversion Rate (fS) Straight Mode ADC-318 ADC-318A De-multiplexed Mode ADC-318 ADC-318A Sampling Delay (TdS) Aperture Jitter (Taj) Integral Linearity Error Diff. Linearity Error S/N Ratio ADC-318 (@fIN = 1kHz) (@fIN = 29.999MHz) ADC-318A (@fIN = 1kHz) (@fIN = 34.999MHz) Error Rate ADC-318 (@fIN = 1kHz) (@fIN = 29.999MHz) (@fIN = 24.999MHz) ADC-318A (@fIN = 1kHz) (@fIN = 34.999MHz) (@fIN = 24.999MHz) POWER REQUIREMENTS Supply Voltage One Power Supply (+AVS, +DVS 1,2) One Power Supply (DGND3) One Power Supply (-DVS) Two Power Supply (+AVS, +DVS 1,2) Two Power Supply (DGND3) Two Power Supply (-DVS) ADC-318 Supply Current (+IS) Supply Current (-IS) ADC-318A Supply Current (+zS) Supply Current (-zS)
11 11 11
3.2 3.0 3.2 3.0 3.5 0
-- -- -- -- -- --
-- -- -- -- -- --
ns ns ns ns ns ns
2.4 -- -- -- 1/Fc 6.5 4.5
-- -- 2 2 1/Fc+1 8 7
-- +0.5 -- -- 1/Fc+2 10 8
Volts Volts ns ns ns ns ns
8
--
--
Bit
Footnote:
Single Supply Dual Supply A/D Clock-A/D Clock and RESET-RESET of ECL/PECL logic inputs. With ADC-318 mounted on a 50x50mm glass fiber base epoxy board, 1.6mm thick.
100 100 100 100 3 -- -- --
-- -- -- -- 4.5 10 -- --
-- -- -- -- 6 -- 0.5 0.5
MHz MHz MHz MHz ns ps LSB LSB
FUNCTIONAL SPECIFICATIONS
(Typical at TA = 25C, VRT = +4V, VRB = +2V, DGND3 = +DVS1= +DVS2 = +AVS = +5V, -DVS = 0V, PECL Logic, unless otherwise specified.) ANALOG INPUTS Input Voltage Input Resistance Input Current Input Capacitance Input Bandwidth VIN = 2Vp-p, -3dB REFERENCE INPUTS Reference Voltage VRT VRB VRT-VRB Reference Resistance Reference Current VRT Offset Voltage VRB Offset Voltage DIGITAL INPUTS ECL, PECL Input Voltage "1" Input Voltage "0" Threshold Voltage Input Current "1" Input Current "0" Voltage Difference TTL Input Voltage "1" Input Voltage "0" Threshold Voltage Input Current "1" Input Current "0" Select Input Voltage "1" Output Voltage "0" Input Capacitance DIGITAL INPUTS A/D Clock Pulse Width (TPW1)
DGND3-1.05 DGND3-3.2
13 13 13
MIN. -- 4 0 -- 150
TYP. +2 to +4 -- -- 21 --
MAX. -- 50 500 -- --
UNITS Volts k A pF MHz
-- -- -- --
46 40 46 40
-- -- -- --
dB dB dB dB
+2.9 +1.4 1.5 75 9.7 2 2
-- -- -- 115 17.4 -- --
+4.1 +2.6 2.1 155 28 15 10
Volts Volts Volts mA mV mV
-- -- -- -- -- --
-- -- -- -- -- --
10-12 10-9 10-9 10-12 10-9 10-9
TPS TPS TPS TPS TPS TPS
11 11 11
-- --
DGND3-1.2
DGND3-0.5 DGND3-1.4
-- -50 -75 0.4 +2.0 -- -- -50 -500 -- -- -- MIN.
-- -- 0.8 -- -- +1.5 -- -- +DVS1 +DGND1 -- TYP.
-- +50 0 -- -- +0.8 -- 0 0 -- -- 5 MAX.
Volts Volts Volts A A Volts Volts Volts Volts A A
+4.75 +4.75 -0.05 +4.75 -0.05 -5.5 125 0.4 110 0.4
+5.0 +5.0 0 +5.0 0 -5.0 145 0.6 150 0.6
+5.25 +5.25 +0.05 +5.25 +0.05 -4.75 185 0.8 185 0.8
Volts Volts Volts Volts Volts Volts mA mA mA mA
pF UNITS
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MDA_ADC-318.B01 Page 2 of 8
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
POWER REQUIREMENTS (cont.) Power Dissipation ADC-318 ADC-318A PARAMETERS Operating Temp. Range, Case ADC-318, 318A Thermal Impedance ja 12 Storage Temperature Range Package Type Weight -20 -- -65 -- +75 C 680 570 780 790 980 960 mW mW
the characteristic impedance of all input/output logic and analog input lines be properly matched. 2. Power supply lines and grounding may effect the performance of the ADC-318 and ADC-318A. Separate and substantial AGND and DGND ground planes are required. These grounds have to be connected to one earth point underneath the device. There are three digital grounds, DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin 12). These DGND 's are separated internally. DGND1 and DGND2 are always connected externally but DGND3 shall be connected differently depending on whether the single or dual power supply mode is used, as explained later. The ADC-318 and ADC-318A have separate +AVs and +DVs pins. It is recommended that both +AVs and +DVs be powered from a single source. Other external digital circuits must be powered with a separate +DVs. Layouts of +AVs and +DVs lines must be separated like the GND lines to avoid mutual interference and are connected to a point through an LC filter. There are two digital supplies +DVs1 (pin 30) and +DVs2 (pins 19, 31, 42). These are also separated internally. These must be tied together outside while in use. Bypassing all power lines with a 0.1uF ceramic chip capacitor and the use of multilayered PC boards is recommended. 3. The analog input terminal (pin 6) has 21pF of input capacitance. The input signal has to be given via a buffer amplifier which has enough driving power. Make lead wires as short as possible and use chip resistors and capacitors to avoid parasitic capacitance and inductance. 4. The use of a buffer amplifier and bypass capacitors is also recommended on the reference input terminals VRT (pin 11) and VRB (pin 2). The analog input range is determined by
5V(A) + + 5V(D) +
62.5 -- C/Watt -- +150 C 48-pin, plastic QFP 0.25 ounces (0.7 grams)
Footnotes:
VIN = +3V +0.07Vrms VIH = DGND3-0.8V VIL = DGND3-1.6V VIH = 3.5V VIL = 0.2V TTL, 0.8 to 2.0V, CL = 5pF DMUX Mode, CL = 5pF; FC = Clock frequency Straight Mode, CL = 5pF CL = 5pF VIN = FS, DMUX mode VIN = FS, DMUX mode, Error >16LSB VIN = FS, Straight mode, Error >16LSB "Times Per Sample" Mounted on 50x50mm, 1.6mm thick glass fiber base epoxy board
11 12
TECHNICAL NOTES
1. The ADC-318 and ADC-318A are ultra high speed full flash A/D converters that have 120MHz and 140MHz sampling rates respectively. The ADC-318 and ADC-318A are fully interchangeable products with the exception of their sampling rates. Their inputs are TTL, ECL and PECL compatible and their outputs are TTL compatible. Obtaining fully specified performance from the ADC-318 and ADC-318A requires that
5V(A) + 5V(D)
5
8
12 19
30 31 42 MSB 40 A BIT 1 39 A BIT 2 38 A BIT 3 37 A BIT 4 36 A BIT 5 VRB +2V
5
8
19
30 31 42 MSB 40 A BIT 1 39 A BIT 2 38 A BIT 3 37 A BIT 4 36 A BIT 5
VRB +2V
2 +
2 +
ANALOG IN +2V to +4V
35 A BIT 6 4 6 7 9 34 A BIT 7 33 A BIT 8 LSB MSB 28 B BIT 1 27 B BIT 2
ANALOG IN +2V to +4V
35 A BIT 6 4 6 7 9 34 A BIT 7 33 A BIT 8 LSB MSB 28 B BIT 1 27 B BIT 2
VRT +4V
26 B BIT 3 11 + 25 B BIT 4 24 B BIT 5 23 B BIT 6 15 22 B BIT 7 21 B BIT 8 LSB 43 44 45 3 10 1 20 29 32 41 TTL CLOCK OUT 5V(D) ECL
VRT +4V
26 B BIT 3 11 + 25 B BIT 4 24 B BIT 5 23 B BIT 6 15 22 B BIT 7 21 B BIT 8 LSB 43 44 45 3 10 1 12 20 29 32 41 TTL CLOCK OUT 5V(D)
A/D CLOCK
13 14 48 47 46
A/D CLOCK
13 14 48 47 46
A/D CLOCK
5V(D) 5V(D)
+ 5V(D)
Figure 2-1: One Power Supply Operation (TTL, PECL)
Figure 2-2: Two Power Supply Operation (ECL)
Note: All capacitors not otherwise designated are 0.1F
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MDA_ADC-318.B01 Page 3 of 8
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
the reference input voltages given to VRT and VRB. Keep the ranges of V within values shown in this data sheet. Standard settings are VRT = +4.0V, V input range from +2 to +4V. This setting can be varied to VRT = +3.5V, VRB = +2V and 1.5V p-p analog input range, depending on your selection of amplifiers which may provide less than +4V output. 5. The ADC-318 and ADC-318A have resistor matrix taps at VRM1 (pin 4), VRM2 (pin 7) and VRM3 (pin 9). These pins provide 1/4, 1/2 and 3/4 full scale of VRT-VRB voltage respectively. These outputs may be used to adjust the integral non-linearity. Bypass these pins to GND with 0.1uF ceramic chip capacitors. 6. A/D CLK input and RSET/RSET inputs are TTL or ECL, PECL (Positive ECL) compatible. Pins are provided individually. TTL or PECL is available with +5V single power applied. ECL is available with 5V dual power applied. The connections of -DVs (pin 1) and DGND3 (pin12) are different depending on the power supply mode used. Refer to Figures 2-1 and 2-2. a. For +5V single power (TTL or PECL) -DVs (pin 1) is connected to DGND. DGND3 (pin 12) is connected to +5V power. b. For 5V dual power (ECL) -DVs (pin 1) is connected to -5V power. DGND3 (pin 12) is connected to DGND. 7. When the A/D CLK is driven with ECL or PECL, A/D CLK (pin 13) and A/D CLK (pin 14) are to be driven by differential logic inputs to avoid unstable performance at critically high speeds. If a risk of unstable performance is acceptable, single logic input can be used opening A/D CLK (pin 14). The A/D CLK pin should be bypassed to DGND with a 0.1uF ceramic capacitor. When connected this way there will be a voltage of DGND -1.2V on the A/D CLK pin. This voltage can not be used as a threshold voltage for ECL or PECL. Input the A/D CLK pulse to pin 15 when TTL is selected. 8. The ADC-318 and ADC-318A have RSET/RSET input pins. An internal frequency half divider can be initialized with inputs to these pins. With ECL or PECL, differential inputs are given to RSET (pin 48) and RSET (pin 47). This function can be achieved with a single input, leaving pin 47 open and bypassing to DGND with a 0.1uF ceramic chip capacitor. The voltage level of pin 47 is the threshold voltage of ECL or PECL. Use RSET (pin 46) for TTL. 9. SELECT (pin 45) is used to set output mode. Connection of this pin to DGND selects the straight output mode and connection to +DVs selects the 1:2 de-multiplexed output mode. The maximum sampling rates are 100MHz for straight mode (For both models, ADC-318 and ADC-318A) and 120MHz (ADC-318) and 140MHz (ADC-318A) for demultiplexed mode. Refer to figure 2-4. There is an application where a multiple number of ADC-318/318A's are used with a common A/D CLK and outputs are in de-multiplexed mode. In this case, the initial conditions of the frequency half divider of each A/D Converter are not synchronized and it is possible that each converter may have one clock maximum of timing lag. This lag can be avoided by giving a common RSET pulse to all converters at power ON. (See Figure 3-3 and 3-4, timing diagrams.) 10.The ADC-318 and ADC-318A have a TTL compatible CLK OUT (pin 43). Since the rising edge of this pulse can provide Setup and Hold time of output data, regardless of the output mode, this signal can be used as synchronization pulse for external circuits. Data output timing is different for the straight mode and the de-multiplexed mode. See the timing chart Figure 3. 11. INV (pin 44) is used to invert polarity of the TTL compatible output data from both A and B ports. Leaving this pin open or connected to +DVs makes the output positive true and connection to DGND makes it negative true logic. See input/output code table, Table 4.
Table 3: Logic Input Level vs. Power Supply Settings
DIGITAL INPUT LEVEL TTL PECL ECL
-DVS 0V 0V -5V
DGND3 +5V +5V 0V
SUPPLY VOLTAGES +5V +5V 5V
Table 4: Digital Output Coding
SIGNAL INPUT VOLTAGE VRT VRM2 VRB
DIGITAL OUTPUT CODE (A,B OUTPUT) INV=1 INV=0 LSB MSB LSB MSB 11111111 10000000 01111111 00000000 00000000 01111111 10000000 11111111
Figure 2-3: A/D Clock Input Connection
Figure 2-4: Digital Input/Output Connections
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MDA_ADC-318.B01 Page 4 of 8
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
3ns min. 6ns max N-1 ANALOG SIGNAL AIN TPW1 A/D CLOCK TPW0 A DATA OUTPUT N+1 Tdo2
2.0V 0.8V 2.0V 0.8V
N+2 Tds N N+1 N+3
N+4 N+5 N+6
N+7
T
6.5ns min. 10ns max. N+3 N+2
B DATA OUTPUT Td clock 4.5ns min. 8ns max. CLOCK OUT Trh RSET 0ns min. Trs 3.5ns min. Trh
2.0V
N
Tdo1 T+2ns max.
2.0V 0.8V
~T
~T
318 TPW1, min 3.2ns TPW0, min 3.2ns 318A 3.0ns 3.0ns
RESET PERIOD Trs
0.8V
Figure 3-1: Demultiplexed Data Output (Select-Pin: +DVS or left open, 120MHz max. Clock Frequency)
Tds N-1
3ns min. 6ns max. N N+2 N+1 N+3 318 TPW1, min 3.2ns TPW0, min 3.2ns 318A 3.0ns 3.0ns
ANALOG SIGNAL AIN TPW1 A/D CLOCK
T TPW0
A DATA OUTPUT
N-4
2.0V 0.8V 2.0V 0.8V
N-3
N-2
N-1
N
B DATA OUTPUT
N-5
N-4 6.5ns min. 10ns max.
N-3
N-2
N-1
Tdo2 CLOCK OUT (inverted A/D CLOCK OUT)
2.0V 0.8V
Td clock RSET
4.5ns min. 8ns max.
Figure 3-2: Straight Data Output (Select-Pin: DGND, 100MHz max. Clock Frequency)
A/D CLOCK
A/D CLOCK
RSET
CLOCK OUT 1
CLOCK OUT 1
DATA OUT 1 (A,B)
DATA OUT 1 (A,B)
CLOCK OUT 2
CLOCK OUT 2
DATA OUT 2 (A,B)
DATA OUT 2 (A,B)
A/D CLOCK A/D CLOCK ADC-318/318A RSET (1)
CLOCK OUT 1 8 8 CLOCK OUT 2 DATA 1 (A, B)
A/D CLOCK A/D CLOCK ADC-318/318A RSET (1)
CLOCK OUT 1 8 8 CLOCK OUT 2 (2) 8 8 DATA 2 (A, B) DATA 1 (A, B)
A/D CLOCK ADC-318/318A A/D CLOCK RSET (2)
A/D CLOCK
8 8 DATA 2 (A, B)
ADC-318/318A RSET A/D CLOCK RSET
Figure 3-3: Parallel Operation without RSET Pulse
Figure 3-4: Parallel Operation using RSET Synchronization
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MDA_ADC-318.B01 Page 5 of 8
ADC-318, ADC-318A
APPLICATION
This device can be used in applications where 3 parallel channels are synchronized. Conversion speed is the highest in the de-multiplexed mode. It is difficult to control timing of three channels at such a high speed. Two practical ways to maintain timing for reading data into the system are given. 1. Clock output of one A/D is used in reading data of other channels Time delay of Clock Output and Output Data are specified as: Td clk (CLK OUT Delay) ; 4.5nSec min., 8.0nsec max. Tdo2 (Output Data Delay); 6.5nSec min., 10nsec max. These values apply over the operating temperature and supply voltage ranges. Timing control of Tset (Setup Time) seems to be very critical. It tends to lead by 0.5nsec as temperature and supply voltages go lower. When A/D converters for 3 channels are used on the same board, temperature and supply voltages tend to change in the same direction and effects caused by these changes are negligible.
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
Tdclk and Tdo2 at Ta=25C , +Vs=+5.0V are; Td clk: 5.0nsec min., 7.5nsec max. Tdo2: 7.0nsec min., 9.5nsec max. So long as devices are located on the same board and take power from the same source, 2.5nsec min. of setup time for data reading can be secured even though temperature and power supply voltages vary. A timing diagram at 140MHz sampling rate is shown in Figure 4a. 2. To read output data of 3 channels into a gate array Both output data lines and each clock output are read into a gate array if the digital circuits after the A/D conversion consist of one high speed gate array. An AND gate is prepared to take the AND of each output signal which is used for reading output data. The slowest rise time clock determines the system clock. Thus adequate setup time is secured. This method can be employed only when a high speed gate array is used. The setup time is delayed by the delay time of the AND gate. The use of a discrete IC gate is not recommended because of its time delay characteristics. See Figure 4b
A/D CLCK Th reset RSET 5.0nS (4.5nS) Td clck min.
7.5nS (8.0nS) CLK OUT Td clck max. 7.0nS (6.5nS) Tdo2 min. Tdo2 max. OUTPUT DATA (A, B) 14nS 9.5nS (10nS) Thold min. 6.5ns Tset min. 2.5nS
*Values in parenthesis are for the entire operating temperature and operating power supply ranges
Figure 4a: Timing diagram 1
A/D CLCK Th reset RSET 5.0nS (4.5nS) Td clck min. 7.5nS (8.0nS) 7.0nS (6.5nS) Tdo2 min. Tdo2 max. OUTPUT DATA (A, B) 9.5nS (10nS) 14nS
CLK OUT
Td clck max.
*Values in parenthesis are for the entire operating temperature and operating power supply ranges
GATE ARRAY CLK (CLK OUT 1, CLK OUT 2, CLK OUT 3)
Tset min. 5.0nS+XnS
Thold min. 6.5nS-XnS
Figure 4b: Timing diagram 2
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MDA_ADC-318.B01 Page 6 of 8
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Figure 5: Evaluation Circuit Diagram 1. The evaluation circuit shown employs PECL logic. Because of this, a 1Vp- p, 0V center, sine wave must be used as the clock input (A/ D CLK) at CN3. 2. When analog signals are taken from the CN1 amplifier input "A" must be left open while "B" is short circuited. The analog input signals at CN1 must be less than 800mVp- p, 0V and zero centered. The +AMP and -AMP supply pins on the input amplifier are normally connected to +/- 5V which, along with the gain of -2 used with the CLC- 404 in this circuit, will limit the amplifiers output dynamic range. To increase the amplifiers output dynamic range the +AMP pin can be connected to +7V and the -AMP connected to -3V. V RT and V RB may require adjustment in this case. 3. When analog signals are input from CN2, the direct input, AC coupling can be achieved by inserting a 0.1F capacitor at" A" and a 10kOhm resistor at "B". It is not necessary to be concerned about the output voltage of the input amplifier. V RT may be limited in this case by NJM3403. The input voltage to the NJM3403 amplifier can be adjusted to correct. Both V RT and V RB can be trimmed.
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
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ADC-318, ADC-318A
MDA_ADC-318.B01 Page 7 of 8
ADC-318, ADC-318A
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
Figure 6: Typical Performance Curve
Fig. 4-1: Supply Current vs. Temperature
170 170
Fig. 4-2: Supply Current vs. Conversion Rate
20
Fig. 4-3: Reference Current vs.Temperature
10-6
Fig. 4-4: Error Rate vs. Conversion Rate ADC-318 ADC-318A
Supply Current (mA)
Error Rate (TPS)
ADC-318A
Supply Current (mA)
160
Reference Current (mA)
ADC-318A
150 140
160
10-7 10-8
ADC-318
150 140
15
ADC-318
fin = Fc/4-1KHz Error> 16LSB
10-9
130 -25
130 0
10 -25
10-10 140
25
75
50
100
140
25
75
160
180
TA -Ambient Temperature (C) Fig. 4-5: SNR+THD vs. Input Signal Frequency 50
SNR+THD (dB)
Conversion Rate (MHz) Fig. 4-6: Allowable Ambient Temperature vs. Air Flow C 90
Analog Input Current (A)
TA -Ambient Temperature (C) Fig. 4-7: Analog Input Current vs.Voltage Inputs
Conversion Rate (MHz) Fig. 4-8: Maximum Conversion Rate vs.Temperature
170 200 VRT = +4V VRB = +2V 100
40 ADC-318: FC=120MHz ADC-318A: FC=140MHz 30
SNR+THD (dB)
Four-layer board 80 Double-layer board 70 Single-layer board
Conversion Rate (MHz)
160 150 140
ADC-318A
ADC-318
130
20 1 5 30 3 10 Input Frequency (MHz) 50
60 0 1 2 3 m/s
0 2
3
4
-25
25
75
VIN Pin Voltage (V) Fig. 4-9: Sine Wave Curvefit Test
1.0000 (256) 0.5000 (192) 0.0000 (128) -0.500 (64) Sine Wave Curvefit Test
8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8
TA -Ambient Temperature (C)
DEVIATION (LSB)
VOLT/ (CODE)
S/N Ratio 48.7dB 7.8 Effective Bits Conditions Sampling Frequency 120MHz Signal Frequency 996kHz 4096 Points
MECHANICAL DIMENSIONS INCES (MM)
.602.016 (15.3) .472 (12.0)
+.016 -.004
0.087 -.006 (2.2) 25
+.014
36
37
24 0.035 .008 (0.9)
0.004 -.004 (0.1)
+.008
.531 (13.5)
0.006 -.002 (0.15)
+.004
48 1 0.031 (0.8) 12
13
ORDERING INFORMATION
ADC-318 ADC-318A 8-bit, 120MHz Flash A/D 8-bit, 140MHz Flash A/D
+.006
0.012 -.004 (0.3)
USA: Canada: UK: France: Germany: Japan: China: Singapore:
Mansfield (MA), Tel: (508) 339-3000, email: sales@murata-ps.com Toronto, Tel: (866) 740-1232, email: toronto@murata-ps.com Milton Keynes, Tel: +44 (0)1908 615232, email: mk@murata-ps.com Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: france@murata-ps.com Munchen, Tel: +49 (0)89-544334-0, email: munich@murata-ps.com Tokyo, Tel: 3-3779-1031, email: sales_tokyo@murata-ps.com Osaka, Tel: 6-6354-2025, email: sales_osaka@murata-ps.com Shanghai, Tel: +86 215 027 3678, email: shanghai@murata-ps.com Guangzhou, Tel: +86 208 221 8066, email: guangzhou@murata-ps.com Parkway Centre, Tel: +65 6348 9096, email: singapore@murata-ps.com
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
www.murata-ps.com email: sales@murata-ps.com ISO 9001 and 14001 REGISTERED
12/30/08
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. (c) 2008 Murata Power Solutions, Inc.
www.murata-ps.com
MDA_ADC-318.B01 Page 8 of 8

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